The field of the invention generally relates to digital-to-analog converters (DACs), and more particularly relates to switched-current-type DACs that generate waveforms of precision amplitude and timing.
As is well known, digital-to-analog converters generate analog signals representative of digital inputs. One type of digital-to-analog converter is commonly referred to as a switched-current-type. That is, a substantially constant current is generated, and the current is switched either to the output or to ground, depending on the state of the digital input. The use of current allows the outputs of many switches to be added by simply tying their outputs together. The resulting summed current can then be converted into a voltage by providing a load resistor.
Switched-current-type DACs are commonly used for high speed applications such as applications having clock rates of 5 MHz and above. One example of a high speed application is an integrated circuit where digital-to-analog converters are used to generate analog versions of output signals which are computed by on-chip digital circuitry. Another example is a phase locked loop which requires a precision sine wave at one point in the process.
In one prior art switched-current-type DAC, a current providing transistor supplies a substantially constant current to a node that branches to an output transistor and a ground path transistor. In particular, the current
providing transistor is a p-type with a drain terminal connected to the node; the output transistor is a p-type with a source terminal connected to the node; and the ground path transistor is an n-type with a drain terminal connected to the node. The digital input is supplied to the gate of the ground path transistor, and determines its state of conduction. The state of conduction of the output transistor is opposite the state of conduction of the ground path transistor. Therefore, depending on the digital input, the substantially constant current is either switched to ground, or alternatively switched to the output of the output transistor.
One drawback of the above described arrangement is that it may generate harmonic distortion. One cause of the distortion results from the switching on of current having a different propagation delay than the switching off of current. In particular, the ground path transistor operates in its linear region. Thus, when the digital input goes high, it can rapidly discharge any capacitance at the node resulting in a very short propagation delay in switching off the output current. However, when the digital input goes low, the capacitance at the node is charged by the current providing transistor which operates in its saturation region. Therefore, the current provided by the current providing transistor is relatively small resulting in a slow charging of the node. Further, the output transistor will not begin to conduct until the node reaches approximately 1 volt above its gate bias voltage. Thus, as compared with the rapid switching off of current after the digital input goes high, the switching on of current has a relatively long propagation delay. The problem of unequal delays between switching on and switching off current can be illustrated by the use of a digital input square wave to generate a precision analog square wave. Rather than obtaining an analog representation of the square wave, an anomalous waveform is generated thereby leading to harmonic distortion.
Another cause of harmonic distortion can arise due to differences in rise and fall times. These output rise and fall times are dependent on the rate at which the output transistor switches from on to off, and vice versa. These switching rates are in turn dependent on the slew rates of the node as the voltage passes through the critical point where the output transistor changes state. The slew rate of the above described arrangement is steeper on the falling edge than on the rising edge. Thus, the output has a quicker fall time than rise time which contributes to harmonic distortion.